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f3(pGhq( P3qGo) Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. ... 44'YaB6 2 R98!
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www.cs.utexas.edu/users/skeckler/pubs/islped03.pdf
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A microprocessor by a pipeline control method with the process of a machine instruction divided into several stages for performing the parallel processing in each stage comprises a register file for h ... The present invention relates to a microprocessor, and more particularly to a pipeline controlled microprocessor.
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www.freepatentsonline.com/5892696.html
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The graphical display represents a flow of the instructions through an internal pipeline in the microprocessor. Execution behavior is selectively displayed based on type of behavior and clock cycle the execution occurred during on the microprocessor.
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www.freepatentsonline.com/y2002/0062208.html
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An instruction pipeline in a microprocessor, comprising a plurality of pipeline units with each of the pipeline units processing instructions. At least one of the plurality of pipeline units receives ... An instruction pipeline in a microprocessor, comprising a plurality of pipeline units with each of the pipeline...
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freepatentsonline.com/20010032307.html
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Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline description/claims ... The Patent Description & Claims data below is from USPTO Patent Application 20060136915, Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline.
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www.freshpatents.com/Method-and-apparatus-for-schedulin...
www.freshpatents.com/Method-and-apparatus-for-scheduling-multiple-threads-for-execution-in-a-shared-microprocessor-pipeline-dt20060622ptan20060136915.php
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Microprocessor Architecture & Pipeline Design ... Maximum Rate Single-Phase Clocking of a Closed Pipeline including Wave Pipelining, Stoppability, and Startability; C.-H. Chang, E. S. Davidson and K. A. Sakallah ; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.
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www.eecs.umich.edu/PPP/publist.html
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An instruction swap is implemented in a dual pipelined microprocessor to make instruction flow smoother upon resource or structural conflicts in executing an instruction. Instructions are accessed in ... 2. In a dual pipelined microprocessor, an instruction fetch ... 3 illustrates the dual pipeline architecture of the core.
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images.freepatentsonline.com/5819060.html
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The present invention recognizes that for most functional units, there will rarely be both single and double precision operations in the pipeline at the same time. Accordingly, the present invention eliminates logic for checking whether a register designation is single or double precision ... 2. A microprocessor comprising:
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www.patentgenius.com/patent/5778247.html
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A microprocessor pipeline arrangement 1 includes a plurality of functional units 2, 3, 4, 5 and 6. Each functional unit 2, 3, 4, 5, 6 also has access to a respective cache memory 7, 8, 9, 10, 11. Threads for processing are received by the first functional unit 2 from an external source 12, and output by an end...
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www.faqs.org/patents/app/20090198972
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