NAND gate - Wikipedia, the free encyclopedia
|
|
The NAND gate is a digital logic gate that behaves in a manner that corresponds to the truth table to the left. A LOW output results only if both the inputs to the gate are HIGH. If one or both inpu...
en.wikipedia.org/wiki/NAND_gate
|
|
NAND logic - Wikipedia, the free encyclopedia
|
|
NAND gates are one of the two basic logic gates (along with NOR gates) from which any other logic gates can be built. Due to this property, NAND and NOR gates are sometimes called "universal gates". H...
en.wikipedia.org/wiki/NAND_logic
|
|
|
You can investigate the behaviour of a single NAND gate using this circuit: ... NAND gate test circuit ... If you have designed a system which contains a NAND gate integrated circuit, it can be convenient and cost-effective to implement other logic functions using spare NAND gates which would otherwise be unused.
|
www.doctronics.co.uk/4011.htm
|
|
|
Sheffer stroke - Wikipedia, the free encyclopedia
|
|
In Boolean functions and propositional calculus, the Sheffer stroke , named after Henry M. Sheffer, written "|" (see vertical bar) or "↑", denotes a logical operation that is equivalent to the negat...
en.wikipedia.org/wiki/Sheffer_stroke
|
|
|
Computer Logic - NAND gate ... ; The output of the NAND gate is a 0 if both inputs are 1 but a 1 if one or the other or both the inputs are 0. ... Note: The NAND is like an AND gate combined with a NOT gate.
|
www.doit.ort.org/course/logic/223.htm
|
|
|
Figure 1.2 Wiring the NAND gate as an inverter ... All digital systems can be constructed by only three basic logic gates. These basic gates are called the AND gate, the OR gate, and the NOT gate. Some textbooks also include the NAND gate, the NOR gate and the EOR gate as the members of the family of basic logic gates.
|
www.ied.edu.hk/has/phys/de/de-lg.htm
|
|
74AC00, 74ACT00 — Quad 2-Input NAND Gate; Absolute Maximum Ratings; Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
|
www.fairchildsemi.com/ds/74/74AC00.pdf
|
|
NAND Gate fabricated with silicon gate CMOS technol-ogy. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the; CMOS low power dissipation. The internal circuit is com-posed of 3 stages, including buffer output, which provide high noise immunity and stable output.
|
www.fairchildsemi.com/ds/74/74VHC00.pdf
|
|
; ; 74F00; Quad 2-input NAND gate; Product specification; IC15 Data Handbook; 1990 Oct 04; INTEGRATED CIRCUITS; ... Quad 2-input NAND gate 74F00; October 4, 1990 3; ABSOLUTE MAXIMUM RATINGS; (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these...
|
www.nxp.com/acrobat_download/datasheets/74F00_2.pdf
|
|
