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Check to see which best fit your needs. If you have any questions, please call for assistance at 1-800-790-7837 or e-mail sales@netmotion.com ... Advisor: Semiconductor Test Wafers ... <<Return to previous page...
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www.netmotion.com/htm_files/adv_wafer.htm
www.netmotion.com/htm_files/adv_wafer.htm
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A single wafer processing apparatus includes a portable processing head that can be a portable module or a movable unit mounted to a supporting machine frame. The processing head has movable fingers adapted to grip a wafer. ... 44. A semiconductor wafer processing head for holding and supporting a wafer,
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www.patentgenius.com/patent/5445172.html
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A single wafer processing apparatus includes a portable processing head that can be a portable module or a movable unit mounted to a supporting machine frame. The processing head has movable fingers adapted to grip a wafer. ... 3. The wafer processing apparatus of claim 2, wherein the shroud includes a...
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www.patentgenius.com/patent/5168887.html
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A microchip fabrication chamber has a pedestal adapted to retain a wafer during processing steps conducted within the chamber. A lift mechanism including a plurality of lift mechanism pins engages and ... In microchip fabrication, processing chambers are used in accomplishing various fabrication steps performed on a wafer.
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www.freepatentsonline.com/6723201.html
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A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and ... In order to reduce the number of processing steps required in the above prior art BiCMOS process, there has been developed...
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www.freepatentsonline.com/6475850.html
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Patent Abstract: A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and thre ... US Patent Issued on March 28, ... Self-aligned all-n+ polysilicon CMOS process ;
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www.patentstorm.us/patents/6043541.html
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memory fail bit map, fail pattern classification, cause estimation, expert knowledge ... In order to determine problematic wafer processing steps rapidly during memory production, the system that classifies failure patterns from memory fail bit maps (FBMs) and estimates the cause of failure is proposed.
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www.nsti.org/procs/MSM2001/12/T67.07
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NEC Electronics has developed a method of connecting logic and memory chips used in high-end cellphones. ... Austin, Texas -- NEC Electronics has a wafer-level packaging technology that it says permits more than 1,000 3-D interconnections between the logic and memory dice used in an image-processing system.
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www.eetimes.com/showArticle.jhtml?articleID=192201420
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