|
www.altera.com/support/devices/pll_clock/jitter/pll-jit...
www.altera.com/support/devices/pll_clock/jitter/pll-jitter.html
|
Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock in the presence of jitter of various magnitudes at different frequencies) ...
|
|
pdfserv.maxim-ic.com/en/an/AN377.pdf
|
receiver jitter tolerance is used as the common ... Jitter tolerance is a measure of the capability of the ... to test the margin of the receiver's jitter tolerance.
|
Jitter - Wikipedia, the free encyclopedia
|
|
en.wikipedia.org/wiki/Jitter
There are standards for jitter measurement in serial bus architectures. The standards cover jitter tolerance, jitter transfer function and jitter generation, with the ...
|
|
|
www.en-genius.net/site/zones/connectivityZONE/technical...
www.en-genius.net/site/zones/connectivityZONE/technical_notes/iot_031609
|
Mar 16, 2009 ... A Practical Guide to Receiver Jitter Tolerance Testing, Part III: Tolerance Test On A PCI Express Add-In Card by Michael Fleischer-Reumann, ...
|
|
www-mount.ece.umn.edu/~sobelman/papers/jitter_isocc05.p...
www-mount.ece.umn.edu/~sobelman/papers/jitter_isocc05.pdf
|
verification methodology for jitter tolerance in high- speed serial-link receiver designs. ... Keywords: serial-link, receiver, jitter tolerance, jitter verification, bit error ...
|
|
|
|
en.wikibooks.org/wiki/Clock_and_Data_Recovery/Jitter_To...
en.wikibooks.org/wiki/Clock_and_Data_Recovery/Jitter_Tolerance,_Jitter_Transfer_Function_and_Generated_Jitter/The_jitter_tolerance_function
|
Aug 17, 2010 ... [edit] The tolerance function. In a feedback loop, like in a PLL for CDR use, the operation will be linear, and the linear modeling will remain valid ...
|
|
ieeexplore.ieee.org/iel5/4/4494641/04494664.pdf?arnumbe...
ieeexplore.ieee.org/iel5/4/4494641/04494664.pdf?arnumber=4494664
|
Abstract—A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit ... the design bottleneck and the predicted jitter tolerance can be enhanced ...
|
|
ieeexplore.ieee.org/iel5/8919/5702426/05634141.pdf?arnu...
ieeexplore.ieee.org/iel5/8919/5702426/05634141.pdf?arnumber=5634141
|
sampling clocks that can tolerate up to 5 psrms clock jitter. In comparison, existing ... extreme jitter tolerance allows for relaxed design of clocking systems, which ...
|
|
www.centellax.com/applications/jtol
|
Jitter tolerance is the measurement of the ability of a receiver to remain at an acceptable bit error rate performance level when various jitter conditions are ...
|
